From: Yong Whang (Ywhang_at_concentric.net)
Date: Thu Mar 04 1999 - 16:19:44 EST
Can you give me the reference for this?
I checked the Intel site (and looked at TX chipset
datasheets), but I can't find any statements alluding
to this. I would think that if the cache controller is turned
off, you'd get like 50% decrease in speed rather than 10% that
you measured.
On another front, I would think that with SDRAM, upper memory
not being cached wouldn't be that bad. I thought that when
EDO and SDRAM first came out, their purpose was to get rid of
L2 cache altogether. It hasn't happened yet, but...
Yong Whang
> >
> > That's actually wrong... According to Intel engineers and I have
> >tested this as well... If the cache controller chipset can only cache 64
> >megs, then it will not cache any ram at all if you go past the limits.
> >This can all be found on Intel's site.
> >
> >
> >Cheers,
> >Vince - vince_at_MCESTATE.COM - vince_at_GAIANET.NET ________ __ ____
> >Unix Networking Operations - FreeBSD-Real Unix for Free / / / / | / |[__ ]
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